This invention relates to circuitry and methods for a high-gain synchronizer. A synchronizer is used to receive an input signal, which may be asynchronous, and to output that signal as a synchronous output. A synchronizer may be used, for example, to receive an asynchronous signal at the input to a synchronous system or it may provide synchronization between two or more asynchronous circuits.
In a synchronous circuit the key components are at least partly controlled by one or more reference clocks. The state of the circuit only changes (at least in major respects) in relation to a reference clock. For example, reference clock may determine when inputs are sampled and when outputs can change. When asynchronous signals are input to synchronous circuits, synchronizers are used to “synchronize” the asynchronous signal to the reference clock.
When an asynchronous signal is sampled by a synchronizer, if the asynchronous signal is out of the sampling window or unresolved, the synchronizer will not be able to determine whether the asynchronous input signal is HIGH or LOW. Thus, the synchronizer may enter a meta-stable state, i.e., an unstable logic state that is neither HIGH nor LOW.
Typically, the synchronizer will automatically resolve itself into a stable state (i.e., HIGH or LOW) after a potentially long period of time in the meta-stable state. However, if the synchronizer does not leave the meta-stable state and settle into a stable state before the next clock triggered transition, a system failure may result from the meta-stable signal being output by the synchronizer and propagated throughout the system. It would therefore be desirable to provide circuitry and methods for a high-gain synchronizer that minimizes the meta-stable resolve time of the synchronizer.
A latch circuit is a circuit that can sample (i.e., receive) an input signal and can maintain and output the HIGH or LOW value of the input signal. A few latches, when connected together with other logic gates, can be used to create a synchronizer.
One typical synchronizer architecture uses a series of two latch circuits connected in a master-slave configuration. In a typical master-slave synchronizer, the first latch circuit (i.e., “the master”) samples the asynchronous input signal at a first clock triggered time and the second latch circuit (i.e., the slave) receives the signal from the first latch circuit and outputs a synchronous output at the next clock triggered time.
If the first latch does not resolve the sampled input signal into a stable state within the reference clock triggered time period, a meta-stable signal will be transferred through to the synchronous output of this synchronizer. It would therefore be desirable to provide circuitry and methods for a high-gain latch circuit that has a greater probability of resolving a meta-stable signal into a stable state before its output is transferred into the logic circuit by the reference clock signal.